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This invention is in the field of integrated circuit manufacturing, and is more specifically directed to the fabrication of transistor gate elements.
A fundamental goal in the integrated circuit art is to form ever-smaller active and passive devices in the circuit. As the dimensions of transistors and other devices decrease, the chip area required to fabricate an integrated circuit of a given level of functionality decreases approximately as the square of the decrease in the critical dimension. Smaller chip area reduces the cost of manufacture for each circuit, or conversely increases the functionality that can be provided by a single integrated circuit of a given size. In addition, the performance of the integrated circuit also tends to increase as the active devices are made smaller.
For metal-oxide-semiconductor (MOS) integrated circuits, a fundamental dimension is the physical width of the transistor gate, which is also often referred to as the gate length. This gate length translates to the length of the conduction channel, from source to drain, of the MOS transistor. Because the transconductance (gain) of the MOS transistor varies inversely with channel length for a given channel width, it is desirable to form MOS transistor gates with ever-decreasing channel lengths. In addition, the smaller gate length devices reduces the integrated circuit chip area, theoretically reducing manufacturing cost while increasing circuit density and functionality. Because of this far-reaching importance, the physical width of the gate electrode (i.e., the xe2x80x9cgate lengthxe2x80x9d, sometimes also referred as the xe2x80x9cgate widthxe2x80x9d) of the smallest MOS transistors in the integrated circuit is also often referred to as the critical dimension (xe2x80x9cCDxe2x80x9d).
Recent improvements in integrated circuit manufacturing technology has resulted in the formation of extremely small transistors, for example with MOS transistor gates now less than 100 nm in length. As is also fundamental in the art, these transistor gates are commonly formed of polycrystalline silicon (polysilicon), sometimes clad with a higher conductivity material such as a refractory metal silicide. The size and locations of transistor gates are defined by photolithography and masked etching of the polysilicon material. However, there is demand for transistors with gate lengths smaller than can be printed with present day lithography, even using phase-shift reticles.
A known technique for defining transistor gates at lengths less than the wavelength of the photolithographic energy involves the xe2x80x9ctrimmingxe2x80x9d of patterned photoresist. FIGS. 1a through 1f illustrate this conventional approach, by way of an example of a device formed at the surface of substrate 2. Typically, substrate 2 will include doped regions, such as wells and perhaps also epitaxial layers. As typical for MOS transistors, gate dielectric layer 3, generally formed of thermal silicon dioxide alone or in combination with silicon nitride, is present between substrate 2 and gate layer 4. Gate layer 4 is typically formed of polysilicon, but alternatively may be formed of a stack of polysilicon with a refractory metal such as tungsten, or may be a layer of refractory metal. Hardmask layer 6 overlies gate layer 4 in this conventional example. Hardmask layer 6 may be formed of silicon dioxide, silicon nitride, silicon oxynitride, or a stack of these materials. In addition, hardmask layer 6 serves also as an anti-reflective layer.
Photoresist layer 8 overlies hardmask layer 6 in this conventional example. In conventional processes, photoresist layer 8 is sensitive to ultraviolet light, for example at a wavelength of 248 nm. Photoresist layer 8 may be either of the positive or negative type; in the case of positive photoresist, the portions exposed to light remain as a mask after developing, while the portions of negative photoresist that are exposed to light are removed after developing. In either case, FIG. 1b illustrates the result of photolithographic exposure of selected portions of photoresist layer 8, through a mask or reticle, following which only selected portions of photoresist layer 8 remain. In the case of FIG. 1b, the remaining portion of photoresist layer 8 has a width wp, as defined by the overlying mask or reticle in the conventional manner. This width wp, which as noted above is also called the critical dimension (CD) value, is wider than the desired eventual gate length, however.
FIG. 1c illustrates the xe2x80x9ctrimmingxe2x80x9d of photoresist layer 8 after its patterning to a CD value wp. The structure is exposed to a chemistry, for example a dry or plasma etch including oxygen as a reactive species, which in effect isotropically etches photoresist layer 8, removing it from its sides and top. This etch is generally a timed etch, with the duration depending upon the desired CD reduction and on the etch rate of photoresist layer 8. Following this trimming etch, photoresist layer 8 has a CD value of wR, on the average, as shown in FIG. 1c. This CD value wR is then the desired gate length to which gate layer 4 is to be etched, and may be on the order of 100 nm or less in modern processes.
Hardmask layer 6 is then etched, using trimmed photoresist layer 8 as a mask, resulting in the structure shown in FIG. 1d. This hardmask etch also tends to remove photoresist 8 to some extent, requiring that the trimmed photoresist layer 8 must be of sufficient thickness to successfully transfer its pattern to hardmask layer 6. Following hardmask etch, the remaining portion of photoresist layer 8 is ashed to remove any source of contaminants for the following processes. Gate layer 4 is etched using the patterned hardmask layer 6 as a mask, resulting in the structure shown in FIG. 1e. Hardmask layer 6 is then removed, leaving gate layer 4 at the desired feature length wR, as shown in FIG. 1f. 
This conventional process has been observed to work reasonably well with conventional 248 nm photoresist, because this class of photoresist is quite stable. However, as noted above, it is desirable to form ever-shrinking gate electrodes, and as such shorter wavelength photolithography is desirable, requiring photoresist that is sensitive to even shorter wavelength UV light.
One class of photoresist that has recently been developed is photoresist that is sensitive to 193 nm UV light. Examples of this photoresist include PAR-707 and PAR-710 available from Sumitomo and AR237 available from JSR. Currently, the 193 nm resists are still immature, in the sense that printed lines are often rough and that these resists are not very stable. It has also been observed that 193 nm photoresist lines shrink when they are measured by top-down scanning electron microscopy (SEM). More importantly, the photoresists are not very resistant to the etch process, as the lines patterned from these photoresists shrink very fast during the etch process. The instability of 193 nm photoresist affects its masking performance. The conventional trimming of 193 nm photoresist, as shown in FIG. 1c, has been observed to result in a photoresist feature that is not thick enough to suitably transfer the pattern to the underlying hardmask or ARC. If the 193 nm photoresist is applied in a thicker layer to address this problem, however, its excessive height cannot be supported at sub-100 nm widths; falling of excessively thick 193 nm photoresist lines has been observed. Excessive photoresist height is also incompatible with the very shallow depth of focus now present in modern deep UV photolithography.
By way of further background, the use of halogen-bearing etch chemistry to etch hardmask materials such as oxides and nitrides, with features masked by 248 nm photoresist elements, is known.
It is therefore an object of this invention to provide a process in which features having critical dimensions that can be smaller than the wavelength of the photolithographic exposure light.
It is a further object of this invention to provide such a process that is suitable for use with 193 nm photoresist.
It is a further object of this invention to provide such a process that can be readily controlled in practice.
It is a further object of this invention to provide such a process that is compatible with conventional process chemistries.
It is a further object of this invention to provide such a process that minimizes the thickness of photoresist required for definition of a hardmask layer.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
The present invention may be implemented in a photolithographic process for forming a critical dimension feature, such as the gate electrode for a metal-oxide-semiconductor (MOS) transistor. A photoresist feature is patterned, for example using photoresist material sensitive to 193 nm light and by exposing this photoresist to 193 nm light through a mask or reticle. The photoresist is overlying a hardmask material, comprised of one or more of an inorganic layers, including one or more layers of silicon dioxide, silicon oxynitride, silicon rich-nitride, and silicon nitride. The photolithographic patterning of the photoresist defines a feature that is wider than the desired eventual width, or critical dimension (CD) value, of the feature. Hardmask etch is then carried out, to define a hardmask feature at this wider CD value. An overetch of the hardmask feature and of the photoresist feature is then performed, to xe2x80x9ctrimxe2x80x9d the hardmask feature and the photoresist to the desired critical dimension value. The photoresist is then removed, and the remaining hardmask used in the etch of the underlying gate layer material, to define a critical dimension feature in that material.